This section enables you to look up the menaing of all State Logic Modeling specification tree symbols.
The following picture represents a typical State Logic Modeling specification tree.
This section provides the symbols and their meanings for all types of features seen in the State Logic Modeling specification trees.
A main block is identified by a red mark.
The following picture represents a typical Block Specification tree.
You can create In/Out ports by activating a customizing option.
The masks on ports appear below.